The present invention relates to on-chip termination impedance, and more particularly, to techniques for providing adjustable on-chip termination impedance on integrated circuits.
Signal reflection can occur on transmission lines when there is a mismatch between the impedance of the transmission line and the impedance of the transmitter and/or receiver. The reflected signal can interfere with the transmitted signal, causing distortion and degrading signal integrity.
To solve this problem, transmission lines are resistively terminated by a matching impedance to minimize or eliminate signal reflection. Input/output (IO) pins on an integrated circuit package are often terminated by coupling external termination resistors to the appropriate IO pins. However, many integrated circuit packages require a large number of termination resistors, because they have a large number of IO pins. Therefore, it is becoming more common to resistively terminate transmission lines using on-chip termination (OCT) to reduce the number of external components.
The Stratix® II field programmable gate array (FPGA) made by Altera, Corporation of San Jose, Calif. has calibrated on-chip termination to support a wide range of high-speed memory interfaces in a single device. Because different memory interfaces require different power supply voltages, input and output buffers are arranged in input/output (IO) banks in order to support memory interfaces flexibly. Each bank has its own power supply independent of other IO banks. Buffers within the same IO bank share the same power supply. Calibrated on-chip source (series) termination (Rs) and parallel termination (Rt) are supported in some of the IO banks to achieve higher memory interface performance.
In the Stratix II FPGA, one calibration circuit controls the on-chip termination impedance in an IO bank, and all of the buffers in the IO bank have the same termination impedance at any particular time. However, class I and Class II memory interfaces typically require different series and parallel termination impedance values. As a result, one IO bank cannot support both class I and class II memory interfaces.
Therefore, it would be desirable to provide techniques for supporting multiple classes of memory interfaces in the same IO bank on an integrated circuit.